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{\bf
Star Technologies VP Series
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{\bf
Pipeline Floating-Point Architecture
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{\bf Architecture:}
The VP-2 has five independent programmable processors.  A separate
processor is dedicated to each of the following functions:
external data flow, internal data flow, 
and synchronization; two are dedicated to arithmetic processing.
A hierarchical memory
system consists of external storage devices, a large main
memory, a high-speed random access partitioned data cache,
and a universal register set.

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The main memory comprises a 320 nsec memory, 8-way
interleaved, composed of four 256K dynamic RAMs with SECDED. It is
expandable to 64 Mbytes in increments of 8 Mbytes. All
main memory is byte addressable (address range 4 Gbytes) and
can be partitioned and protected at multiples of 16 Kbytes.
Memory access time is 40 nsec (per 32-bit word).  The random
access data cache memory consists of 6 banks of 32K 32-bit
words for a total of 768 Kbytes. During each machine cycle,
four cache references are permitted: three by the arithmetic
processor and one by the storage/move processor.
Information flow is from host to main memory to cache to
functional unit to cache to memory to host.


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Other features:\\
\&gt;80 nsec clock cycle.\\
\&gt;2 $\mu$ CMOS.\\
\&gt;32-bit floating-point arithmetic, pipelined functional units, both with\\
\&gt;\&gt; 2 adders,\\
\&gt;\&gt;  2 multipliers, and a 480 nsec divide/square root functional unit.\\
\&gt;Ambient air cooled\\
\&gt;Size 19" x 21" x 29"\\

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A data interchange unit permits one of 16 operands to be
selected for each arithmetic input register.  During each
machine cycle, three cache banks may be referenced, one loop
control operation computed, four arithmetic operations
started, and a conditional branch executed.

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The 25 Mbyte I/O channel supports 3 device adapters; 12.5
Mbyte/sec data transfer rate.

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{\bf Configuration:}
The VP-2 Series of array processors are designed to attach to a
more general-purpose computer or host via bus.

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{\bf Software:}\\

\&gt;  Fortran-like control language (APCL)\\
\&gt;\&gt;  Macro assembler\\
\&gt;\&gt;  Simulator/debugger and Linker\\
\&gt;\&gt;  Library Maintenance Program\\
\&gt;\&gt;  Applications Library available.

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{\bf Performance:}
100 Mflops peak in single-precision (32-bit)
arithmetic for convolution and matrix operations.

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{\bf Status:} \$95,000 base price.


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{\bf Contact:}
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Star Technologies Inc.\\
515 Shaw Road\\
Sterling, VA 22170\\
703-689-4400\\
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Technical: Phil Cannon\\
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