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{\bf
CDC CYBERPLUS
}


\noindent
{\bf
Ring Bus Architecture
}


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\noindent
{\bf Architecture:}
This is a multiple parallel processor system.  It grew from
the Flexible Processor Project and the subsequent Advanced Flexible
Processor Project (AFP), used in military applications since
1976.  The machine is based on ring technology with an 800
Mbits/second transfer rate, with a read and a write possible
between processors at this sustained rate.

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\noindent
There are two CYBERPLUS processor modes: 16-bit integer and
32- and 64-bit floating point.
The integer processor has 15 independent
functional units capable of 8-, 16- an 32-bit working; each
processor has a 20-nsec cycle time.  The floating-point
processor is an extension of the integer one through the
addition of three floating-point functional units capable of
32- and 64-bit precision, with rated maximum performance of
65 Mflops (103 in 32-bit mode).

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\noindent
Each processor contains 2048 Kbytes of memory which can be
expanded to 4096 Kbytes.  A crossbar architecture allows the
output of one functional unit to go to any or all other
functional units in one machine cycle and permits all
functional units to fire every cycle.  The 
independent functional units are as follows:

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\noindent
\begin{tabbing}
aaa\= bbb\=  \kill

\&gt; - 1 program unit\\
\&gt; - 9 I/O units including 4 read/write 16-bit memory units\\
\&gt; - 2 read/write 64-bit memory units, 2 ring port I/O units,\\
\&gt; - 5 integer/Boolean units (2 add/subtract, 1 multiply, and\\
\&gt;\&gt;     2 shift Boolean)
\end{tabbing}

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\noindent
Floating point: 1 add/subtract, 1 multiply, 1 divide/square root
connected by an additional crossbar.
Floating-point units can run simultaneously with fixed-point ones.

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\noindent
Each instruction can initiate multiple functional units.


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\noindent
{\bf Configuration:}
Up to 16 rings can be connected to a CYBER 800 computer
(each connected through a channel ring port) with up to 16
CYBERPLUS processors per ring. Within this ring all
processors can operate autonomously and may execute each
clock cycle.  Processor Memory Interface allows direct
reading and writing of the memory of any processor by
another processor on the ring every machine cycle.  Central
Memory Interface (CMI) for transfer of data to host. The
central memory ring is 64 bits wide with an 80 nsec
cycle time, and this provides a direct transfer of 64 bits
between the CYBER and a CYBERPLUS processor.  Data transfers
are controlled by the system ring and will be direct
memory-to-memory transfers with the HPM memory on the CYBERPLUS
processors.  Two rings connect the processors:
the system ring and the application ring.  The ring packet
has 13 bits of control information and 16 bits of data. A
function code in the ring packet can determine whether
access to other memories (one or several) is direct or
indirect, the latter requiring the acceptance by the target
processor.

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\noindent
There are three distinct memory systems:

\begin{tabbing}
aaa\=bbb\=   \kill
\&gt;  1. 4K 16-bit data memory: 4 independent bipolar data\\
\&gt;\&gt;    memories with a one-cycle read/write.\\
\&gt;  2. 256K 64-bit high-performance data memory: 4 banks with\\
\&gt;\&gt;    4-cycle memory access, expandable to 512K 64-bit words\\
\&gt;\&gt;    with 8 banks.\\
\&gt;  3. Program Instruction Memory with 4096 200-bit words. Each\\
\&gt;\&gt;    machine cycle, the instruction memory fetches and\\
\&gt;\&gt;    initiates the execution of one or all of the parallel\\
\&gt;\&gt;    functional units. When the floating-point option is in\\
\&gt;\&gt;    use, the size of these memory words increases to 240 bits.\\
\&gt;\&gt;    The program instruction memory is expandable to 16K words. \\
\end{tabbing}


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\noindent
{\bf Software:}
The host CDC 170 Series 800 (under NOS 2) loads code into
the processors, transmits data from host to processors, and
starts and stops processor's task.  Software includes a
cross assembler (MICA), a CYBERPLUS instructor load
simulator (ECHOS), and an ANSI 77 Fortran cross-compiler.


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\noindent
64-bit floating point is 14 decimal accurate with a range of
$10 ^ {-293 }$ to $ 10 ^ {+322 }$.

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\noindent
32-bit is 7 decimal accurate with range $10 ^ {-39}$ to $10 ^ {+37}$.

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\noindent
{\bf Performance:}
Claimed performance of 64 CYBERPLUS systems linked to a
single Control Data 170 Series 800 is 16 billion
calculations per second on signal data applications. Change
detection algorithm for image processing is about 100 times
faster than on a CDC 7600.

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\noindent
{\bf Status:}
Announced formally on October 4, 1983;
floating-point hardware and software delivered in first
quarter 1985.  Fortran compiler available for research
activities fourth quarter 1984 and released April 1985.

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\noindent
Cost: Entry-level CYBERPLUS base processor is priced at
\$470,000, which includes a 16-bit integer unit and 2048 Mbytes
of memory. With all available options the price is \$1.6
million.

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\noindent
{\bf Contact:}
\begin{flushleft}
Martin Ferrante\\
Control Data Corporation\\
CYBERPLUS Marketing\\
P.O. Box O\\
HQS09B\\
Minneapolis, MN 55440\\
800-828-8001 ext 88\\

\vspace {.1in}
B. Lawrence\\
Control Data Limited\\
3 Roundwood Avenue\\
Stockley Park\\
Uxbridge\\
Middlesex UB11 1AG\\
England\\
01-848-1919
\end{flushleft}
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